Semiconductor memory device and its test method as well as test circuit

ABSTRACT

The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array  30.  Then, a test signal TE 1  is set “ 1 ” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit  51.  A first address for test is applied to an address terminal  21,  whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal 21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array 30 are checked to decide the presence or absence of any abnormality.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,and its test method as well as a test circuit integrated in thesemiconductor memory device.

[0003] 2. Prior Art

[0004] It is necessary for the semiconductor memory device to make avariety of test before shipment, for which purpose in may cases, a testcircuit has previously been provided in the semiconductor memory device.

[0005]FIG. 1 is a block diagram of a semiconductor memory device withsuch a test circuit, for example, one structural example of a pseudoSRAM (a pseudo static random access memory). The structure of thisconventional semiconductor memory device is disclosed in JapaneseLaid-open Patent Publication No. 1-125796. This semiconductor memorydevice has the following structure.

[0006] A memory array 1 has a plurality of memory cells which storedata. A sense amplifier 2 is connected to the memory cell array 1 foramplifying data from the memory array 1. A column I/O circuit 3 becomesconnected to a bit line of the memory cells in the memory array 1 forselectively activating this bit line. A column decoder 4 receives aninput of external addresses A8-A15 and is connected to the column I/Ocircuit 3, so that the external addresses A8-A15 enter into the columnI/O circuit 3, whereby the column I/O circuit 3 selectively activates abit line based on these external addresses A8-A15. Further, a mainamplifier/write buffer 5 is provided for writing or reading data

[0007] A multiplexer 8 is connected to an output side of a refreshcontrol circuit 12 and also connected to an output side of an addresscounter 9, so that in accordance with an output signal from a refreshcontrol circuit 12, the multiplexer 8 selects any of externally enteredexternal addresses A0-A7 and the refresh address outputted from theaddress counter 9. An output side of the multiplexer 8 is connected to arow decoder 7 so that selected one of the external addresses A0-A7 orthe refresh address is inputted into the row decoder 7. The row decoder7 is connected to a word driver 6 so that any one of the externaladdresses A0-A7 or the refresh address is inputted into the word driver6. The word driver 6 is connected to a word line of the memory cell inthe memory array 1, so that the word driver 6 selectively activates theword line based on the external addresses A0-A7 or the refresh address.

[0008] A test mode deciding circuit 10 receives an input of a /CE signal(/ representing a negative logic signal) or a /RFSH signal, so that thetest mode deciding circuit 10 decides whether the mode is a test mode ornot, and outputs a test signal which indicates the decided result. Anoutput control circuit 14 is connected to an output side of the testmode deciding circuit 10, so that the output control circuit 14 iscontrolled by the test signal outputted from the test mode decidingcircuit 1 and outputs an I/O output switching signal. Further, theoutput control circuit 14 is connected to the timer circuit 11 and theI/O output switching circuit 15, so that for test, the output controlcircuit 14 controls the I/O output switching circuit 15, whereby afrequency divided signal outputted from the timer circuit 11 is suppliedthrough the I/O output switching circuit 15 to an I/O terminal.

[0009] The refresh control circuit 12 receives inputs of the /CE signaland the /RFSH signal, so that if those signals satisfy predeterminedconditions, then the refresh control circuit 12 performs refreshoperations of the memory cells. The above-described timer circuit 11outputs a refresh request signal periodically at a constant timeinterval. The timer circuit 11 is connected to the refresh controlcircuit 12 so that the refresh request signal is inputted into therefresh control circuit 12. A timing generating circuit 13 is connectedto this refresh control circuit 12 for receiving an input of the refreshcontrol signal outputted from the refresh control circuit 12 and alsoreceives external inputs of an /RE signal, an /OE signal and a CSsignal, so that the timing generating circuit 13 outputs an internalsynchronizing signal and controls operations of the entirety of thecircuit.

[0010] In such configurations, if the /RFSH signal is a low level (L) ata time when the /CE signal is transited from a high level (H) to a lowlevel (L), then the test mode deciding circuit 10 decides that the modeis the test mode. In this case, the test mode deciding circuit 10transmits a signal through the output control circuit 14 and outputsthis signal for oscillating the timer circuit 11, whereby the refreshcontrol circuit 12 operates the address counter 9 and controls themultiplexer 8, so that the refresh address (n-address) of the addresscounter 9 is outputted from the multiplexer 8 as the row address of thememory cells. The external addresses A8˜A15 are entered as the columnaddresses to the column decoder 4.

[0011] In the above manners, a memory cell of a designated address bythe row address of n-address and the column addresses A8˜A15, so that aread out operation of data content of the cell is accomplished.Accordingly, the specific data have previously been written into thecell of this address so that in the test mode, the content in the cellis directly read out, thereby accurately deciding whether or not datahave correctly been written and read out. Namely, it is possible toaccurately decide whether or not the timer circuit 11 and the addresscounter 9 normally operate.

[0012] When the mode is set into the test mode, the timer circuit 11 isoscillated, wherein the frequency divided signal outputted from thetimer 11 is supplied through the output switching circuit 15 to the I/O7terminal. Checking the frequency divided output signal results in anaccurate decision on whether or the timer circuit 11 normally operates.

[0013] Issue to be Solved by the Invention

[0014] The above described pseudo SRAM is a semiconductor memory devicewhich has the same memory cell structure as the DRAM (dynamic randomaccess memory), and has the same condition in use as the SRAM, whereinit is necessary to internally perform a self-refresh of the memory cellsevery when a predetermined time passes.

[0015] The address of the memory cell to be self-refreshed or therefresh address is generated by the inside of the circuit, for whichreason the refresh address is completely irrelevant to the externallysuppleid read/write addresses.

[0016] In the worst case, for example, it is possible that adjacent twoof the word lines are sequentially activated, wherein the common bitline is activated. In this case, it is possible that any memorymalfunction appears due to an insufficient pre-charge and a slightleakage of current under a field insulating film.

[0017] The test conducted by the above-described semiconductor memorydevice is, however, only to check the operations of the timer circuit 11and also sequentially read out the data of the memory cells bysequentially changing the counted value of the address counter 9. It isimpossible to intentionally check the operations or make the test in theworst case which is likely to cause the above-described malfunction.

[0018] In consideration of the above-described circumstances, an objectof the present invention is to provide a semiconductor memory devicewhich is capable of checking operations under any conditions.

[0019] A further object of the present invention is to provide a testcircuit integrated in a semiconductor memory device and capable ofchecking operations under any conditions.

[0020] A furthermore object of the present invention is to provide atest method capable of checking operations a semiconductor memory deviceunder any conditions.

[0021] Means for Solving the Issue

[0022] The present invention was made to solve the above-issues, andprovides a test method for a semiconductor memory device with aplurality of memory cells which need refreshes, wherein during a testoperation, there is accomplished, at least one time, a combination of: aread/write process for reading or writing the memory cell based on afirst address externally entered; and a refresh process for refreshingthe memory cells based on a second address externally entered.

[0023] The combination of two processes may optionally be that after therefresh process is made, then the read/write process is made.

[0024] The combination of two processes may optionally be that after theread/write process is made, then the refresh process is made.

[0025] The combination of two processes may optionally be made in onecycle.

[0026] The read/write process and subsequent the refresh process andfurther subsequent the read/write process may optionally be accomplishedin one cycle.

[0027] The two processes may optionally be made at a common columnaddress and at row addresses close to each other.

[0028] The two processes may optionally be made at a common columnaddress and at row addresses adjacent to each other.

[0029] The test method for a semiconductor memory device may optionallyfurther include a process of discontinuing the refresh of the memorycell based on a third address generated inside of the semiconductormemory device, in response to a switch of the semiconductor memorydevice from a normal operation mode to a test mode.

[0030] When the normal operation mode is switched to the test mode basedon a mode switching signal externally entered, the test address may beselected from the third address and the test address, so that therefresh of the memory cell based on the third address may bediscontinued.

[0031] The semiconductor memory device may optionally be switched fromthe normal operation mode to the test mode based on a mode switchingsignal externally entered.

[0032] When the normal operation mode may be switched to the test modebased on the mode switching signal externally entered, the test addressmay be selected from the third address and the test address, so that therefresh of the memory cell based on the third address may bediscontinued.

[0033] The test operation may optionally be that a set of plural rowaddresses is subject to the refresh operation with fixing a columnaddress and sequentially changing row addresses.

[0034] The test operation may optionally be that a set of all rowaddresses is subject to the refresh operation with fixing a columnaddress and sequentially changing row addresses.

[0035] The test operation may optionally be that a set of respective allrow addresses for each of plural blocks divided from a memory cell arrayis subject to the refresh operation with fixing a column address andsequentially changing row addresses.

[0036] Both the first address and the second address may optionally beexternally entered every changes of the row address.

[0037] The first address may optionally be externally entered everychanges of the row address, while only an initial address of the secondaddress is externally entered, and the second address may beautomatically changed in accordance with a predetermined constant ruleevery changes to the row address.

[0038] A predetermined increment of the second address may optionally bemade every changes to the row address.

[0039] A hold test of a memory cell to be subject to the test may bepreviously tested and a predetermined test pattern may be written,before the two processes may be accomplished.

[0040] The present invention provides a semiconductor memory devicehaving a plurality of memory cells which need refresh, a circuit elementfor supplying a first address, and an access address control circuit forrefreshing the memory cell based on an address, wherein thesemiconductor memory device further has: a circuit for holding a secondaddress externally entered; and a refresh address switching circuitelectrically coupled to the circuit element for supplying the firstaddress and also coupled to the circuit for holding the second address,and in a normal operation mode, the refresh address switching circuitsupplies the first address to the access address control circuit, and ina test mode, the refresh address switching circuit supplies the secondaddress to the access address control circuit.

[0041] The refresh address switching circuit may optionally comprise aselecting circuit which is electrically coupled to the circuit elementfor supplying the first address and also coupled to the circuit forholding data, and in the normal operation mode, the selecting circuitselects the first address, and in the test mode, the selecting circuitselects the second address.

[0042] The selecting circuit may optionally comprise a multiplexerelectrically coupled to the circuit element for supplying the firstaddress and also coupled to the circuit for holding data.

[0043] The semiconductor memory device may optionally further include: acontrol circuit electrically coupled to the refresh address switchingcircuit for supplying the refresh address switching circuit a controlsignal which switches between the normal operation mode and the testmode.

[0044] The control circuit may optionally comprise a test entry circuit.which switches between the normal operation mode and the test mode inresponse to a predetermined external signal.

[0045] The circuit for holding the second address may optionallycomprise a data storage device electrically coupled to the refreshaddress switching circuit.

[0046] The semiconductor memory device may optionally further include anaddress inverting circuit electrically coupled to between the circuitfor holding data and the refresh address switching circuit for invertingthe second address outputted from the data storage device, and supplyingthe same to the refresh address switching circuit.

[0047] The circuit element for supplying the first address mayoptionally comprise a refresh address generating circuit connected tothe refresh address switching circuit.

[0048] The present invention provides a test circuit for a semiconductormemory device, the circuit having a plurality of memory cells which needrefresh and a circuit element for supplying a first address based on aninternal signal, wherein the test circuit has: a circuit for holding asecond address externally entered; and a refresh address switchingcircuit electrically coupled to the circuit element for supplying thefirst address and also coupled to the circuit for holding the secondaddress, and in a normal operation mode, the test circuit supplies thefirst address to the access address control circuit, and in a test mode,the test circuit supplies the second address to the access addresscontrol circuit.

[0049] The refresh address switching circuit may optionally comprise aselecting circuit which is electrically coupled to the circuit elementfor supplying the first address and also coupled to the circuit forholding data, and in the normal operation mode, the selecting circuitselects the first address, and in the test mode, the selecting circuitselects the second address.

[0050] The selecting circuit may optionally comprise a multiplexerelectrically coupled to the circuit element for supplying the firstaddress and also coupled to the circuit for holding data.

[0051] The test circuit may optionally further include: a controlcircuit electrically coupled to the refresh address switching circuitfor supplying the refresh address switching circuit a control signalwhich switches between the normal operation mode and the test mode.

[0052] The control circuit may optionally comprise a test entry circuitwhich switches between the normal operation mode and the test mode inresponse to a predetermined external signal.

[0053] The circuit for holding the second address may optionallycomprise a data storage device electrically coupled to the refreshaddress switching circuit.

[0054] The test circuit may optionally further include an addressinverting circuit electrically coupled to between the circuit forholding data and the refresh address switching circuit for inverting thesecond address outputted from the data storage device, and supplying thesame to the refresh address switching circuit.

[0055] The test circuit may optionally be integrated in thesemiconductor memory device, or be separated from the semiconductormemory device and be mounted on a same chip as the semiconductor memorydevice. In either configuration, there is no problem, provided that thetest circuit is electrically coupled to the semiconductor memory device,and signals and addresses are transmitted between the test circuit andthe semiconductor memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0056]FIG. 1 is a block diagram showing the structural example of theconventional semiconductor memory device.

[0057]FIG. 2 is a block diagram showing a structure of one embodiment ofthis invention.

[0058]FIG. 3 is a timing chart describing a normal operation in theembodiment.

[0059]FIG. 4 is a timing chart describing a test operation in theembodiment.

[0060]FIG. 5 is a flow chart describing a test operation in theembodiment.

[0061]FIG. 6 is another flow chart describing a test operation in theembodiment.

[0062]FIG. 7 is a circuit diagram showing one example of a circuitconfiguration of a multiplexer included in the circuit configuration ofFIG. 2.

MODE FOR CARRYING OUT THE INVENTION

[0063] One embodiment of the present invention will, hereinafter, bedescribed with reference to the drawings. In the following embodiment,one structural example is shown, wherein the test circuit is integratedin the semiconductor memory device.

[0064]FIG. 2 is a block diagram showing a circuit configuration of asemiconductor memory device (pseudo SRAM) in accordance with thisembodiment. FIG. 3 is a timing chart of output signals from respectivecircuits of the semiconductor memory device shown in FIG. 2. The circuitconfiguration of the semiconductor memory device (pseudo SRAM) will bedescribed with reference to FIG. 2, while the output signals from therespective circuits will be described with reference to FIG. 3. Aread/write address Add is applied to an address terminal 21 fromoutside. A terminal 22 is applied with a first test signal TE1 fromoutside. A terminal 23 is applied with a second test signal TE2 fromoutside. Only the terminal 22 is a terminal dedicated for the test. Theterminal 21 is applied with the read/write address Add in the normaloperation. The terminal 23 is also applied with an output enable signalOE in the normal operation and serves as a terminal for receiving thetest signal.

[0065] An address transition detector circuit (ATD circuit) 25 isconnected to the terminal 21 for receiving an input of the read/writeaddress Add which was applied to the terminal 21 from outside, so thatthe address transition detector circuit 25 detects any transition of rowaddress data AddR (see FIG. 3) included in this address data Add. If atleast one bit in all bits of the row address data AddR is transitioned,then the address transition detector circuit (AD circuit) 25 detects thetransition and outputs a pulse signal ATD.

[0066] A row control circuit 26 is connected to an output side of theaddress transition detector circuit (ATD circuit) 25, so that, based onthe pulse signal ATD outputted from the address transition detectorcircuit (ATD circuit) 25, the row control circuit 26 generates andoutputs a row enable signal RE, a sense enable signal SE and a columncontrol signal CC. As shown in FIG. 3, the row enable signal RE is apules signal which rises at a rising time and a falling time of thepulse signal ATD, and then falls after a predetermined time passes fromthose times. The sense enable signal SE is a signal delayed by apredetermined time from the row enable signal RE. Even not shown in thedrawing, the column control signal CC is a later one of two sequentialrow enable signals RE, namely a signal delayed by a predetermined timefrom the pulse signal based on the falling of the signal ATD. When thesecond text TE2 is “0” or in the low level, the row control circuit 26does not output the row enable signal RE.

[0067] A column control circuit 27 is connected to the row controlcircuit 26 for receiving the column control signal CC outputted from therow control circuit 26 and further delays the column control signal CC,and outputs a column enable signal CE.

[0068] A memory cell array 30 has a similar structure as a memory cellarray of DRAM. A row decoder 31 is connected to word lines of the memorycell array 30 and also connected to the row control circuit 26, so thatat a timing when the row enable signal RE outputted from the row controlcircuit 26 becomes “1”, the row decoder 31 selectively activates a wordline of the memory cell array 30, wherein the word line corresponds torow address data RA1 outputted from a multiplexer (MUX) 32.

[0069] A sense amplifier 33 is connected to each bit line of the memorycell array 30 and also connected to the row control circuit 26, so thatthe sense amplifier 33 activates each bit line of the memory cell array30 at a timing when the sense enable signal SE outputted from the rowcontrol circuit 26 becomes “1”.

[0070] A column decoder 35 is connected to the above-described terminal21 and the column control circuit 27, so that at a timing when a columnenable signal CE outputted from the column control circuit 27 becomes“1”, the column decoder 35 decodes column address data AddC included inthe address data Add applied to the terminal 21, so that a senseamplifier corresponding to this decode result is connected through anI/O buffer 36 to an input/output data terminal 37.

[0071] A refresh control circuit 40 is a circuit for self-refresh of thememory cell array 30. This refresh control circuit 40 is connected to anoutput side of the address transmission detector circuit (ATD circuit)25 for receiving the pulse signal ATD and outputs a pulse signal and areset signal at a time when the pulse signal AID falls. The refreshcontrol circuit 40 is further connected to a timer 42 and a refreshaddress generating circuit 41, so that the refresh control circuit 40outputs a pulse signal at a time when the pulse signal ATD falls, andthe pulse signal as outputted is entered into the refresh addressgenerating circuit 41, and the reset signal is entered into the timer42. The refresh address generating circuit 41 receives the pulse signaland makes an increment by one of the refresh address RFAD.

[0072] The above-described refresh control circuit 40 detects, based ona timer signal from the timer 40 that any output of the pulse signal ATDfrom the address transition detector circuit (ATD circuit) does notappear for a predetermined time, so that the refresh control circuit 40outputs a self-refresh signal RF. An output side of the refresh controlcircuit 40 is connected to the row control circuit 26, so that theself-refresh signal RF as outputted is entered into the row controlcircuit 26.

[0073] Further, a test circuit 50 for testing a pre-shipment completeproduct receives inputs of first and second test signals which wereapplied to the terminals 22 and 23, and the test circuit 50 outputs anoutput signal T3 and a refresh address RA. The refresh control circuit40 is connected to the test circuit 50 for receiving an input of theoutput signal T3 and then outputting a signal M and a self-refreshsignal RF, whereby a self-refresh of the memory cell array 30 isconducted.

[0074] The test circuit 50 comprises a data store circuit 51, aninverter circuit 52, a test entry circuit 53 and a multiplexer 54. Thedata store circuit 51 captures and outputs row address data AddRincluded in the address data Add which were applied to the terminal 21,at a timing when the signal T1 outputted from the text entry circuit 53rises. The row address data AddR as outputted is entered into theinverter circuit 52. The inverter circuit 52 inverts respective bitsoutputted from the data store circuit 51 and outputs a test address TA.The test entry circuit 53 is connected to the terminals 22 and 23, andthe test entry circuit 53 outputs signals T1˜T3 based on the first andsecond test signals TE1 and TE2 which were applied to those terminals.The multiplexer 54 selects any one of the test address TA from theinverter circuit 52 and the refresh address RFAD from the refreshaddress generating circuit 41, based on the signal T2 from the testentry circuit 53, and the multiplexer 54 outputs a signal RA This signalRA is entered into the above-described multiplexer 32.

[0075] The test mode operation and the normal operation of theabove-described semiconductor memory device will be describedseparately.

[0076] Initially, the normal operation will be described with referenceto FIG. 3. In this mode, the test signal TE1 is set at “0”, whereby thesignals T1˜T3 outputted from the test entry circuit 53 become “0”. Inthe normal operation, the test circuit 50 does not operate, and thus theoperation is substantially the same as the semiconductor integratedcircuit free of any integration of the test circuit.

[0077] In this state, when data “A1” as the row address data AddR areapplied to the terminal 21, the ATD circuit 25 detects that the data“A1” were applied, whereby the pulse signal ATD (“1”) is entered intothe row control circuit 26 and the multiplexer 32. The multiplexer 32receives the pulse signal ATD (“1 ”) and outputs data RA from themultiplexer 54 as the row address data RA1. The row address data RA1 arethen entered into the row decoder 31.

[0078] Since the signal T2 is “0”, the multiplexer 54 outputs therefresh address RFAD which is supplied through the multiplexer 32 to therow decoder 31, provided that the refresh address RFAD was “R1”.

[0079] On the other hand, the row control circuit 26 receives the pulsesignal ATD and outputs the row enable signal RE. This row enable signalRE is entered into the row decoder 31. The row decoder 31 receives thisrow enable signal RE and activates a word line designated by theabove-described address data “R1”.

[0080] Subsequently, the row control circuit 26 outputs the sense enablesignal SE which is then supplied to the sense amplifier 33, whereby thesense amplifier is activated. After the sense amplifier 33 is activated,a memory cell connected to a word line designated by the above-describedrow address data “R1” is refreshed.

[0081] When the pulse signal ATD falls, the refresh control circuit 40supplies a pulse signal to the refresh address generating circuit 41,whereby the refresh address RFAD is incremented and becomes “R1+1”.Simultaneously, the timer 42 is reset. When the pulse signal ATD falls,the multiplexer 32 supplies the row decoder 31 the data AddR (data “A1”at this time) as the row address data RA1. When the pulse signal ATDfalls, the row control circuit 26 supplies the row enable signal RE tothe row decoder 31.

[0082] The row decoder 31 receives the row enable signal RE andactivates a word line of the memory cell array 30, wherein the word lineis designated by row address data “A1” outputted from the multiplexer32. Subsequently, the row control circuit 26 outputs the sense enablesignal SE which is then supplied to the sense amplifier 33, whereby aword line corresponding to the address data “A1” of the sense amplifier33 is activated.

[0083] Subsequently, the column control circuit 27 supplies the columnenable signal CE to the column decoder 35. The column decoder 35receives the column enable signal CE and decodes a column address dataAddC, so that a sense amplifier corresponding to this decode result isconnected through the I/O buffer 36 to the input/output data terminal37. In case of read operation, data stored in the memory cell array 30are transmitted through the sense amplifier 33 and the I/O buffer 36 tothe data terminal 37. In case of write operation, data on the dataterminal 37 are written into the memory cell array 30.

[0084] As described above, in accordance with the semiconductor memorydevice of FIG. 2, after the read/write address data Add are applied tothe address terminal 21, a refresh of a memory cell connected to a wordline designated by the refresh address RFAD is made and subsequently aread/write operation of the memory cell array 30 is made based on theaddress data Add.

[0085] If the read/write operation of the memory cell array 30 has notbeen conducted within a predetermined time period, then the timer 42supplies the pulse signal to the refresh control circuit 40. The refreshcontrol circuit 40 receives the pulse signal and conducts theself-refresh. Namely, the refresh signal RP is supplied to the rowcontrol 26, and the signal M of “1” is supplied to the multiplexer 32.The multiplexer 32 receives this signal M and supplies the row decoder31 the refresh address RFAD (data “R1+1 ”) as the row address data RA1.

[0086] The refresh signal RF is supplied to the row control circuit 26,and then the row control circuit 26 supplies the row enable signal RE tothe row decoder 31 and subsequently supplies the sense enable signal SEto the sense amplifier 33, whereby a memory cell connected to a wordline corresponding to the row address data “R1+1” is refreshed similarlyto the above case.

[0087] The above descriptions are the normal operations of thesemiconductor memory device shown in FIG. 2.

[0088] Subsequently, the pre-shipment test operation using the testcircuit 50 will be described with reference to FIG. 4, which is a timingchart for describing the test operation.

[0089] A variety of patterns as test patterns for the pre-shipment testmay be considered. As one example, it is possible to conduct the test,wherein a read/write “address B” is “X1”, and “refresh address A” is aninverted address “/X1” of “X1”. The following descriptions will be madeby taking one example that the read/write “address B” is “X1” and“refresh address A” is the inverted address “/X1”.

[0090] In this pre-shipment test, at a time t1, the test signal TE1rises up to “1”, whereby the test entry circuit 53 enters into the testmode, and thereafter the test entry circuit 53 recognizes any signalsapplied to the terminal 23 to be the second test signal TE2.Subsequently, the address data “X1” are applied to the terminal 21. At atime t2, the second test signal TE2 applied to the terminal 23 falls to“0”.

[0091] The second test signal TE2 falls to “0”, then the test entrycircuit 53 detects this fall, and rises the signal T1 to “1”. The signalT1 rises to “1”, and upon this rising, the data store circuit 51captures the address data AddR applied to the address terminal 21,namely the address data “X1”, whereby the address data “X1” are thensupplied to the inverter circuit 52. The inverter circuit 52 inverts theaddress data “X1” and outputs the same as data “/X1”. The invertedaddress data “/X1” are supplied as the test address data to themultiplexer 54.

[0092] In the above embodiment, as described above, the inverter 52 isinterposed between the data store circuit 51 and the multiplexer 54.Thus, it is possible to conduct the refresh at the inverted address“/X1” and the read/write operation at the address “X1” without anychange to the address data “X1” to be applied to the address terminal21. Namely, in the read or write operation, the multiplexer 32 selectsthe address “X1” which was entered through the address terminal 21 sothat the read or write operation is made at the address “X1”. In therefresh operation, the multiplexer 32 selects the inverted address “/X1”which was entered through the address terminal 21 and inverted by theinverter 52, so that the read or write operation is made at the invertedaddress “/X1”.

[0093] The address data “X1” supplied from an external tester may beused commonly for both the read or write operation and the refreshoperation. This may make it easy to prepare he test patterns and alsomake a test program simple.

[0094] In case that the inverter 52 is not provided, it is necessarythat the inverted address data “/X1” are applied as the refresh addressto the address terminal 21. Every when the read or write address ischanged, then the inverted address as the refresh address is needed tobe applied to the address terminal 21. As a result, the test program islikely to be complicated. This is more remarkable as a scale of thememory cell array is large.

[0095] Accordingly, it is preferable to provide the inverter 52 forallowing the address data applied to the address terminal 21 to be usedcommonly for both the read or write operation and the refresh operation.The inverter 52 is mere circuit design choice and not essential for thetest circuit. For example, depending upon the test pattern, it is notnecessary that the read or write address B is “X1”, the refresh addressA is the inverted address “/X1” of “X1”. In this case, it is unnecessaryto provide, on purpose, the inverter 52.

[0096] At a time t3, the address data “X1 as the read/write address “B”as the address data AddR are applied to the address terminal 21. Theaddress data “X1 are applied to the address terminal 21, and asdescribed above, the pulse signal ATD is outputted from the ATD circuit25. The outputted pulse signal MD is entered into the row controlcircuit 26. Since at this time, the test signal TE2 is “0”, then the rowenable signal RE and the sense amplifier enable signal SE are notoutputted from the row control circuit 26.

[0097] The second test signal TE2 rises to “1” at a time t4, that apredetermined time (a time slightly longer than a pulse width of thepulse signal ATD) passes from the time t3 when the address data “X1” wasapplied to the terminal 21. The test signal TE2 rises to “1”, and thenthe test entry circuit 53 detects this rising, and the signals T2 and T3rise to “1”. The signal T2 rises to “1”, then the multiplexer 54 outputsthe test address data TA as the address data RA.

[0098] At this time t4, the signal 13 rises, and the refresh controlcircuit 40 detects this rising, and supplies the self-refresh signal RFto the row control circuit 26 and also supplies the signal M to themultiplexer 32. The signal M is entered into the multiplexer 32, and themultiplexer 32 supplies the address data AddR (the data “X1” at thistime) to the row decoder 31. When the signal RF is entered into the rowcontrol circuit 26, the second test signal TE2 has already risen to “1”.Thus, the row enable signal RE is outputted from the row control circuit26. This row enable signal RE is then entered into the row decoder 31,whereby a word line designated by the address data “X1” is activated.Subsequently, the sense enable signal SE is outputted from the rowcontrol circuit 26, and then he sense amplifier 33 is activated, and theread/write is made to the word line designated by the address data “X1”.

[0099] At a time t5, address data “C” are applied to the addressterminal 21. When the address data “C” are applied to the addressterminal 21, then the ATD circuit 25 detects this, and supplies thepulse signal ATD (“1” to the multiplexer 32 and the row control circuit26. The multiplexer 32 selects an output from the multiplexer 54, namelythe test address TA (the address data “/X1” as the refresh address A atthis time), and then supplies the selected data to the row decoder 31.As the pulse signal AD is supplied to the row control circuit 26, thesecond test signal TE2 has been “1”, and thus the row enable signal REis outputted from the row control circuit 26, and the row enable signalRE as outputted is then entered into the row decoder 31, whereby theword line designated by the address dara “/X1” is activated.Subsequently, the sense enable signal SE is outputted from the rowcontrol circuit 26, and the sense amplifier 33 is activated, whereby thememory cell connected to the word line designated by the address data“/X1” is refreshed.

[0100] At a time t6, the pulse signal ATD falls to “0”, then themultiplexer 32 supplies the address data AddR (data C at this time) tothe row decoder 31. When the pulse signal ATD falls to “0”, and the rowenable signal RE is outputted from the row control circuit 26. The rowenable signal RE as outputted is entered into the row decoder 31,whereby a word line designated by the address data “C” is activated.Subsequently, the sense enable signal SE is outputted from the rowcontrol circuit 26, and the sense amplifier 33 is activated, and aread/write operation of the word line designed by the address data “C”is made.

[0101] As described above, the test circuit 50 shown in FIG. 2 iscapable of previously setting the test-purpose refresh address (theabove address data “A” in the data store circuit 51. Since the refreshaddress “A” previously set in the data storage circuit 51 could havebeen previously recognized, it is possible that the test-purposeread/write addresses (the above-described address data “B”, “C”)adjacent to this refresh address are entered from outside, so that thetest under any conditions, for example, the worst condition, mayintentionally and surely made.

[0102] A word line is designated based on the refresh address “A” forrefreshing the memory cell and subsequently an adjacent word line to theabove word line is designated based on the test-purpose read/writeaddress for the read/write operation, so that the test is intentionallymade, wherein adjacent two of the word lines are sequentially activatedwith fixing a common bit line. Namely, it is possible to verify whetheror not any malfunction of the storing operation appears under anyconditions, for example, under the worst condition with an insufficientpre-charge or a slight leakage of current under a field insulating film.

[0103] The pre-shipment test using the above-described test circuit 50will be described with reference to the flow chart of FIG. 5.

[0104] If a chip originally has any stationary defect or has a memorycell with a bad hold characteristic, then the test for refresh operationis no sense, for which reason the holding test is needed to be carriedout previously (Step S1). The holding test may be made in the known testsequences similarly to those of the test taken place for thegeneral-purpose DRAM.

[0105] Namely, data are written into memory cells of the memory cellarray 30 and the refresh remains inhibited for a predetermined time,before data are read out from the memory cells, wherein thepredetermined time (or refresh cycle) is adjusted so that the read outdata correspond to the written data, thereby deciding the hold times ofthe memory cells. This test is conducted for all of the memory cells, sothat it is possible to decide the refresh cycle based on the shortesthold time of the memory cells. The inhibition of the refresh operationmay be made by entry of the control signal into the refresh controlcircuit 40.

[0106] Subsequently, in order to make a post-test decision on whether ornot the refresh operation and the read/write operation are madecorrectly, the test patterns have previously been written into thememory cell array 30 (Step S2). In order to investigate the normality ofthe refresh operation and the read/write operation, the test patternwith all bits of “1” is used.

[0107] An optional hold time is set (Step S3). Subsequently, the firsttest signal TE1 is risen to “1” to set the circuit into the test mode(Step S4).

[0108] Subsequently, the refresh address data (“A”) are applied to theaddress terminal 21, to cause the test signal TE2 to be fallen to “0”,whereby the address data “A” are written into the data store circuit 51(Step S5).

[0109] Address data (“B”) are applied to the address terminal 21,wherein the address data (“B”) designate a word line which is connectedto the same sense amplifier as a word line which is designated by theaddress data “A” (Step S6).

[0110] After the predetermined time has passed, similarly to the above,Address data (“C”) are applied to the address terminal 21, wherein theaddress data (“C”) designate a word line which is connected to the samesense amplifier as a word line which is designated by the address data“A” (Step S7).

[0111] Through the above processes, as shown in FIG. 4, the normalaccess to the address “B”, the refresh operation at the address “A” andthe normal access to the address “C” are sequentially conducted.

[0112] Subsequently, data stored in the memory cells connected to therespective word lines designated by the above addresses “A”, “B” and “C”are read out and then checked (Step S8). If the result of the check is“NG” (Step S9), then the test is finished and the chip is disposed (StepS10). If the result of the check is “PASS” (Step S9), then it is decidedwhether or not the entirety of the test has been completed (Step S11).If the result of the decision is “NO”, then it returns to the step S5.

[0113] Thereafter, the above steps S5˜S8 are repeated until the resultof decision on, whether or not the entirety of the test has beencompleted, becomes “YES”. The test is made for all combinations of therow addresses with the common sense amplifier. For testing the allcombinations of the row addresses, it is possible that a word line isfixed as a refresh word line, while the word lines of the normalaccesses before and after the refresh operation are sequentiallychanged. For example, a word line is fixed as a refresh word line, whilethe word lines of the normal accesses before and after the refreshoperation are sequentially changed from the top one to the bottom one.

[0114] The above test process will be repeated by fixing another wordline as the refresh word line until all of the word lines have beenselected as the refresh word line, whereby the test is made for all ofthe test patterns.

[0115] In case that the memory cell array 30 is divided into a pluralityof blocks, each of which is allocated with each sense amplifier, thetest may be made for all combinations of the row addresses in the eachblock.

[0116] Practically, it take a long time to make the test for allpatterns. It is possible alternatively to make the test with disciplinedaddresses. Namely, initially, all patterns are subject to the test, butafter any tendency appears, some of the patterns may be omitted. For thetest techniques for not only the DRAM but also the normal memory, theremay be a pattern which is likely to find out the defects. For example, acombined test of test methods such as mating or gallop may be effective.Needless to say, it is preferable to conduct the test for all patterns.

[0117] In the above-described embodiment, the test is made by changingthe row address, independently from the column addresses. In the normalaccesses, the bit line is connected through a column switch to a databus. The data of the memory cells may be influenced depending on how toopen the bit lines and pre-charge. Accordingly, it is preferable toconduct the test with further changing the column addresses.

[0118] In this case, it is possible to add a process for settingoptional column address data AddC following to the step S5 in FIG. 5.FIG. 6 is a flow chart of the test to be conducted by changing not onlythe row addresses but also the column addresses.

[0119] The steps S1˜S5 are conducted similarly to the above. Thereafter,data “D” as the column address data AddC are applied to the addressterminal 21. The column decoder 35 decodes the column address data AddC,and a sense amplifier corresponding to the decoded result is connectedthrough the I/O buffer 36 to the input/output data terminal 37. Namely,the bit line is designated by the column address data AddC (Step S12).Address data (“B”) are applied to the address terminal 21, wherein theaddress data (“B”) designate a word line which is connected to the samesense amplifier as a word line which is designated by the address data“A” (Step S6).

[0120] After the predetermined time has passed, similarly to the above,Address data (“C”) are applied to the address terminal 21, wherein theaddress data (“C”) designate a word line which is connected to the samesense amplifier as a word line which is designated by the address data“A” (Step S7).

[0121] Through the above processes, the normal access to the address“B”, the refresh operation at the address “A” and the normal access tothe address “C” are sequentially conducted with fixing a bit linedesignated by the column address AddC.

[0122] The same test will be repeated by changing the bit linesdesignated. In addition to the refresh row address, the column addressis also changed for the test in order to investigate whether or not thedata of the memory cells may be influenced depending on how to open thebit lines and pre-charge.

[0123] In accordance with the above embodiment, enabling to optionallyset the address from the outside of the chip increases the flexibility.In other words, designation of all of the addresses should be made fromthe outside. This is complicated and inconvenience method. It is,however, possible that the above normal access addresses “B” and “C”only are given from the outside, while the refresh address “A” isautomatically incremented inside of the circuit, so as to save theprogramming work for the test program. In this case, it is possible toincrement the refresh address by utilizing the address counter in therefresh address generating circuit 41.

[0124] In case that the test-purpose refresh address (the above addressdata “A”) is automatically incremented inside of the test circuit 50,the increment is made in accordance with the predetermined rule, forwhich reason it is possible to previously recognize the incrementedrefresh address (address data “A+1”). Thus, it is possible that thetest-purpose read/write addresses (the above-described address data “B”,“C”) adjacent to this incremented refresh address are entered fromoutside, so that the test under any conditions, for example, the worstcondition, may intentionally and surely made.

[0125] Namely, the word line is designated by the automaticallyincremented refresh address for taking place the refresh operation ofthe memory cell, and subsequently the word lines adjacent to the aboveword line are designated by the test-purpose read/write address fortaking place the read/write operation, thereby enabling the test underany optional conditions, for example, the worst condition withoutdesignating all of the addresses from the outside.

[0126] In the above embodiment, the multiplexer 54 receives the refreshaddress RFAD outputted from the refresh address generating circuit 41and also receives the test address TA outputted from the data storecircuit 51, and, in the normal operation mode, the multiplexer 54selects the refresh address RFAD generated in the circuit based on thecontrol signal T2 from the test entry circuit 53, and in the test mode,the multiplexer 54 selects the test address TA entered from the outside.In response to the change from the normal operation mode to the testmode, the supply of the refresh address RFAD generated inside of thecircuit is discontinued, so that in the test mode, it is prevented thatthe refresh operation is made based on the refresh address RFADgenerated inside of the circuit.

[0127] One example of. the circuit configuration of the above-describedmultiplexer 54 is shown in FIG. 7. The multiplexer 54 has a first gatefurther comprising a first n-type transistor N1 and a first p-typetransistor P1, a second gate further comprising a second n-typetransistor N2 and a second p-type transistor P2, and an inverter INV1.The multiplexer 54 also has a test address input unit for the testaddress TA which was outputted from the data store circuit 51 andentered through the inverter 52, and a refresh address input unit forreceiving an input of the refresh address RFAD outputted from therefresh address generating circuit 41, a control signal input unit forreceiving an input of the signal T2 outputted from the test entrycircuit 53, and an output unit of the circuit.

[0128] The first gate comprising he first n-type transistor N1 and thefirst p-type transistor P1 is provided between the test address inputunit and the output unit. The second gate comprising the second n-typetransistor N2 and the second p-type transistor P2 is provided betweenthe refresh address input unit and the output unit.

[0129] Further, the control signal input unit is connected to a gate ofthe first n-type transistor N1, a gate of the second p-type transistorP2, and an input side of the inverter INV1. An output side of theinverter INV1 is connected to a gate of the first p-type transistor P1and a gate of the second n-type transistor N2.

[0130] The signal 12 outputted from the test entry circuit 53 is enteredinto the gate of the first n-type transistor N1 and the gate of thesecond p-type transistor P2, while the inverted signal of the signal T2is entered into the gate of the first p-type transistor P1 and the gateof the second n-type transistor N2.

[0131] Accordingly, in the normal operation mode, the signal T2 is inthe inactive state or in the low level “L”, whereby the first gatecomprising the first n-type transistor N1 and the first p-typetransistor P1 is closed, while the second gate comprising the secondn-type transistor N2 and the second p-type transistor P2 is opened. Thetest address TA is not outputted, while the refresh address RFAD isoutputted, so that the refresh operation is made of the memory cellbased on the refresh address RFAD generated inside of the circuit in thenormal operation mode.

[0132] In the test mode, the signal T2 is in the active state or in thehigh level “H”, whereby the first gate comprising the first n-typetransistor N1 and the first p-type transistor P1 is opened, while thesecond gate comprising the second n-type transistor N2 and the secondp-type transistor P2 is closed. The test address TA is outputted, whilethe refresh address RFAD is not outputted, so that the refresh operationis made under the worst condition of the memory cell based on the testaddress TA entered from the outside of the circuit in the test mode. Theabove-multiplexer 54 is mere one example of the circuits which have afunction of selecting any one of the test address TA and the refreshaddress RFAD based on the control signal generated upon transitionbetween the normal operation mode and the test mode. It is notunnecessary to limit the circuit to this multiplexer. It is no problem,provided that the row address for access for the read/write operation inthe test mode and the row address for access for the refresh operationare surely controllable from the outside.

[0133] In the above embodiment, there was described one case that afterthe refresh operation is made, then the read/write operation is made.The present invention is also applicable to another case that after theread/write operation is made, then the refresh operation is made.

[0134] As described above, the test-purpose refresh address (the aboveaddress data “A”) may previously be set in the data store circuit 51 andthe refresh address “A” may previously be recognized, for which reasonit is possible that the test-purpose read/write addresses (the aboveaddress data “B” and “C” are entered from the outside of the circuit, sothat word lines adjacent to the word line designated by the refreshaddress “A” are designated based on the test-purpose read/writeaddresses for taking place the test-purpose read/write operations, andsubsequently the word line is designated by the refresh address “A” fortaking place the refresh operation of the memory cell. This allows thatthe test is intentionally and surely made under the worst conditions,wherein adjacent two of the word lines are sequentially activated with afixed common bit line.

[0135] In the above descriptions, one example of the word conditions isthat the adjacent two of the word lines are sequentially activated witha fixed common bit line. Notwithstanding, this case is not necessarilythe worst case. For example, the worst case might be another case thatnon-adjacent two word liens are sequentially activated with a fixedcommon bit line. The worst case might be still another case that the bitlines are different and not common. Further, the tests not only underthe worst condition but also under other bad conditions might, in case,be needed. In accordance with the present invention, the refreshaddresses for the test operation are controllable in the tester side, sothat the test operation can surely be made under any conditions.

[0136] Further, in the embodiment, the description has been made in casethat the test circuit is integrated in the semiconductor memory device.It is possible, if necessary, that the test circuit and thesemiconductor memory device are separated from each other but mounted onthe same chip. In either structures, there is no problem, provided thatthe test circuit and the semiconductor memory device are electricallycoupled to each other for transmitting signals and addresses between thetest circuit and the semiconductor memory device.

[0137] The present invention should not be limited to the structures ofthe above described embodiment. A variety of modification to theembodiment may be available unless the subject matter of the presentinvention is changed.

EFFECT OF THE INVENTION

[0138] As described above, in accordance with the present invention, inthe test operation, the test-purpose refresh address is stored in theinternal data storage device, so that the test-purpose addressescorresponding to adjacent word lines to a word line designated by thetest-purpose refresh address are applied to the address terminal,whereby the read/write operation is made based on the test-purposeaddress and subsequently the refresh operation of the memory cell isconducted based on the test-purpose refresh address stored in the datastorage device.

[0139] Otherwise, the refresh operation of the memory cell is conductedbefore the read/write operation is made. Namely, the test may beconducted for any address combinations. This allows checking operationsin the worst case.

What is claimed is:
 1. A test method for a semiconductor memory devicewith a plurality of memory cells which need refreshes, wherein during atest operation, there is accomplished, at least one time, a combinationof: a read/write process for reading or writing said memory cell basedon a first address externally entered ; and a refresh process forrefreshing said memory cells based on a second address externallyentered.
 2. The test method for a semiconductor memory device as claimedin claim 1, wherein said combination of two processes is that after saidrefresh process is made, then said read/write process is made.
 3. Thetest method for a semiconductor memory device as claimed in claim 1,wherein said combination of two processes is that after said read/writeprocess is made, then said refresh process is made.
 4. The test methodfor a semiconductor memory device as claimed in any one of claims 1-3,wherein said combination of two processes is made in one cycle.
 5. Thetest method for a semiconductor memory device as claimed in claim 1,wherein said read/write process and subsequent said refresh process andfurther subsequent said read/write process are accomplished in onecycle.
 6. The test method for a semiconductor memory device as claimedin claim 1, wherein said two processes are made at a common columnaddress and at row addresses close to each other.
 7. The test method fora semiconductor memory device as claimed in claim 6, wherein said twoprocesses are made at a common column address and at row addressesadjacent to each other.
 8. The test method for a semiconductor memorydevice as claimed in claim 1, further including a process ofdiscontinuing the refresh of said memory cell based on a third addressgenerated inside of said semiconductor memory device, in response to aswitch of said semiconductor memory device from a normal operation modeto a test mode.
 9. The test method for a semiconductor memory device asclaimed in claim 8, wherein when the normal operation mode is switchedto the test mode based on a mode switching signal externally entered,the test address is selected from said third address and said testaddress, so that said refresh of said memory cell based on said thirdaddress is discontinued.
 10. The test method for a semiconductor memorydevice as claimed in claim 1, wherein said semiconductor memory deviceis switched from the normal operation mode to the test mode based on amode switching signal externally entered.
 11. (amended) The test methodfor a semiconductor memory device as claimed in claim 10, wherein whenthe normal operation mode is switched to the test mode based on the modeswitching signal externally entered, the test address is selected fromsaid third address generated inside of said semiconductor memory deviceand said test address, so that said refresh of said memory cell based onsaid third address is discontinued.
 12. The test method for asemiconductor memory device as claimed in claim 1, wherein said testoperation is that a set of plural row addresses is subject to saidrefresh operation with fixing a column address and sequentially changingrow addresses.
 13. The test method for a semiconductor memory device asclaimed in claim 12, wherein said test operation is that a set of allrow addresses is subject to said refresh operation with fixing a columnaddress and sequentially changing row addresses.
 14. The test method fora semiconductor memory device as claimed in claim 12, wherein said testoperation is that a set of respective all row addresses for each ofplural blocks divided from a memory cell array is subject to saidrefresh operation with fixing a column address and sequentially changingrow addresses.
 15. The test method for a semiconductor memory device asclaimed in claim 1, wherein both said first address and said secondaddress are externally entered every changes of the row address.
 16. Thetest method for a semiconductor memory device as claimed in claim 1,wherein said first address is externally entered every changes of therow address, while only an initial address of said second address isexternally entered, and said second address is automatically changed inaccordance with a predetermined constant rule every changes to the rowaddress.
 17. The test method for a semiconductor memory device asclaimed in claim 16, wherein a predetermined increment of said secondaddress is made every changes to the row address.
 18. The test methodfor a semiconductor memory device as claimed in claim 1, wherein a holdtest of a memory cell to be subject to the test is previously tested anda predetermined test pattern is written, before said two processes areaccomplished.
 19. A semiconductor memory device having a plurality ofmemory cells which need refresh, a circuit element for supplying a firstaddress, and an access address control circuit for refreshing saidmemory cell based on an address, wherein said semiconductor memorydevice further has: a circuit for holding a second address externallyentered; and a refresh address switching circuit electrically coupled tosaid circuit element for supplying said first address and also coupledto said circuit for holding said second address, and in a normaloperation mode, said refresh address switching circuit supplies saidfirst address to said access address control circuit, and in a testmode, said refresh address switching circuit supplies said secondaddress to said access address control circuit.
 20. (amended) Thesemiconductor memory device as claimed in claim 19, wherein said refreshaddress switching circuit comprises a selecting circuit which iselectrically coupled to said circuit element for supplying said firstaddress and also coupled to said circuit for holding said secondaddress, and in said normal operation mode, said selecting circuitselects said first address, and in said test mode, said selectingcircuit selects said second address.
 21. (amended) The semiconductormemory device as claimed in claim 20, wherein said selecting circuitcomprises a multiplexer electrically coupled to said circuit element forsupplying said first address and also coupled to said circuit forholding said second address.
 22. The semiconductor memory device asclaimed in claim 19, further including: a control circuit electricallycoupled to said refresh address switching circuit for supplying saidrefresh address switching circuit a control signal which switchesbetween said normal operation mode and said test mode.
 23. Thesemiconductor memory device as claimed in claim 22, wherein said controlcircuit comprises a test entry circuit which switches between saidnormal operation mode and said test mode in response to a predeterminedexternal signal.
 24. (amended) The semiconductor memory device asclaimed in claim 19, wherein said circuit for holding said secondaddress comprises a data storage device electrically coupled to saidrefresh address switching circuit.
 25. (amended) The semiconductormemory device as claimed in claim 19, further including an addressinverting circuit electrically coupled to between said circuit forholding said second address and said refresh address switching circuitfor inverting said second address outputted from said circuit forholding said second address, and supplying the same to said refreshaddress switching circuit.
 26. The semiconductor memory device asclaimed in claim 19, wherein said circuit element for supplying saidfirst address comprises a refresh address generating circuit connectedto said refresh address switching circuit.
 27. (Amended) A test circuitfor a semiconductor memory device, said circuit having a plurality ofmemory cells which need refresh and a circuit element for supplying afirst address based on an internal signal, wherein said test circuithas: a circuit for holding a second address externally entered; and arefresh address switching circuit electrically coupled to said circuitelement for supplying said first address and also coupled to saidcircuit for holding said second address, and in a normal operation mode,said test circuit supplies said first address to an access addresscontrol circuit, and in a test mode, said test circuit supplies saidsecond address to said access address control circuit.
 28. (amended) Thetest circuit as claimed in claim 27, wherein said refresh addressswitching circuit comprises a selecting circuit which is electricallycoupled to said circuit element for supplying said first address andalso coupled to said circuit for holding said second address, and insaid normal operation mode, said selecting circuit selects said firstaddress, and in said test mode, said selecting circuit selects saidsecond address.
 29. (amended) The test circuit as claimed in claim 28,wherein said selecting circuit comprises a multiplexer electricallycoupled to said circuit element for supplying said first address andalso coupled to said circuit for holding said second address.
 30. Thetest circuit as claimed in claim 27, further including: a controlcircuit electrically coupled to said refresh address switching circuitfor supplying said refresh address switching circuit a control signalwhich switches between said normal operation mode and said test mode.31. The test circuit as claimed in claim 30, wherein said controlcircuit comprises a test entry circuit which switches between saidnormal operation mode and said test mode in response to a predeterminedexternal signal.
 32. The test circuit as claimed in claim 27, whereinsaid circuit for holding said second address comprises a data storagedevice electrically coupled to said refresh address switching circuit.33. (Amended) The test circuit as claimed in claim 27, further includingan address inverting circuit electrically coupled to between saidcircuit for holding said second address and said refresh addressswitching circuit for inverting said second address outputted from saidcircuit for holding said second address, and supplying the same to saidrefresh address switching circuit.
 34. The test circuit as claimed inclaim 27, wherein said test circuit is integrated in said semiconductormemory device.
 35. The test circuit as claimed in claim 27, wherein saidtest circuit is separated from said semiconductor memory device and ismounted on a same chip as said semiconductor memory device.